In FIG. 1 typical topology of a DC-DC up-converter 100 is depicted. Basically, an input voltage Vin is supplied to the converter core 110. When the switch S1 is conducting the current through the coil L ramps up. When the switch S2 is conducting the current is forwarded to the output capacitor C2. A digital controller 150 measures the output voltage Vout at the capacitor C2 by a sensing circuit 130. The sensing circuit 130 generates a control signal as input for the controller 150 from the actual output signal Vout. By controlling the switches S1 and S2 the controller 150 regulates Vout to a desired value. Thereby, the switches S1 and S2 are never conducting at the same time. For deriving a feedback signal, which indicates an error between the present output signal and a desired output signal value, for the control circuit 150 of the converter 100, one or more comparators may be used in the sensing circuit 130. The feedback signal may indicate that the output voltage is within, above or below a desired window which is defined for the output voltage. For that purpose a quantized feedback or control signal, respectively, is sufficient. The controller regulates the switching of the switches S1, S2 based on the feedback signal such that the output voltage Vout is always within this window.
In the following with reference to FIG. 2, a circuit arrangement is shown for defining the respective error windows in order to derive applicable control signals for a digital control unit of the DC-DC-converter. Two windows, each with a high level and a low level are used: the first narrower window is herein called ‘small signal’ window Ws, the other ‘large signal’ window W1. This implies that a total of four comparators OPLWs, OPHWs, OPLW1 and OPHW1 are used to create these four (window) levels. However, these comparators need to be accurate and this usually means they are current consuming and use a relatively large area of silicon.
In FIG. 2 it shall be assumed that Vout of a switching power supply, for example the DC-DC-converter of FIG. 1, is desired to be 2.5 V. Vout is sensed by a resistive divider 210 of resistors RI, RII with the ratio 4:1, that is the output of the resistive divider 210 should be 625 mV, if Vout of the converter is as desired. Next, the output of the divider 210 is compared to 4 levels around 625 mV. The respective comparator outputs VH20, VH05, VL05, and VL20 are used as inputs for the digital controller controlling the switches of the converter. That is during operation the digital controller tries to regulate the (divided) output voltage Vout into the small signal window Ws between the levels VL05−VH05, in the example of FIG. 2 within the range of 620 mV to 630 mV. For bigger load steps (changes of the load and the needed load current) the controller tries to regulate the (divided) output voltage Vout to be within the large signal window W1 between the levels VL20−VH20, here 605 mV to 645 mV. FIG. 3 depicts the large signal window W1 (VL20−VH20), and the small signal window Ws (VL05−VH05).
A disadvantage of the circuit of FIG. 2 is that the four comparators OPLWs, OPHWs, OPLW1 and OPHW1 have to be very accurate. This implies these comparators use a lot of silicon area and high bias currents. Further, the four comparators OPLWs, OPHWs, OPLW1 and OPHW1 form a considerable capacitive load for the resistive divider 210 at Vout. Together with the divider 210 having a relatively high impedance for efficiency reasons, the bandwidth is limited. As consequence thereof, the control loop may not react adequately fast to changes of the output voltage Vout in cases of sudden load steps. Moreover, the ‘distance’ between the error window levels is not fixed. Depending on the offsets of the comparators OPLWs, OPHWs, OPLW1 and OPHW1 the windows can be smaller or larger than intended, affecting the stability of the control loop, especially in case of very small window sizes. Therefore, the offsets of the comparators OPLWs, OPHWs, OPLW1 and OPHW1 are the main reason in cases where the actual window sizes differ from the intended window sizes.
For instance, it is assumed that the two small signal window comparators have an error of ±2 mV, corresponding to a 99.4% error level (so-called 4-sigma error). These offsets can be considered as not correlated. Accordingly, the maximum distance between VL05 and VH05 is VH05−VL05max=2×5 mV+√{square root over (2 mV2+2 mV2)}=12.8 mV and the minimum distance between VL05 and VH05 is VH05−VL05 max=2×5 mV−√{square root over (2 mV2+2 mV2)}=7.2 mV. The effects on the small signal window of these errors are illustrated in FIGS. 4a and 4b for the two possible worst case scenarios. When the small signal window becomes to small instability of the control loop will become a problem.
It is therefore, one object of the present invention to provide a circuit arrangement and method by which the afore-discussed problem can be avoided.
The afore mentioned object of the invention is solved by a feedback. Accordingly, the feedback circuit, for generating a control signal representing the relation of a signal to be controlled relative to predetermined limits of at least one error signal window, comprises signal detecting means, a detected signal connected to error amplifying means for amplifying the error between the detected signal and a first reference signal, an output error signal of the error amplifying means connected to at least a first comparator means and second comparator means each configured to compare the error signal with one of the upper limit and lower limit of the at least one error signal window.
The feedback circuit may further comprising means for generating error window reference signals for providing the upper limit and the lower limit of the at least one error signal window. The means for generating error reference signals can be implemented as a resistive divider connected to a second reference signal and the resistive divider can be configured to provide as outputs the upper limit and the lower limit of the at least one error signal window. In a further development the circuit comprises two error signal windows a small window for small changes to the signal to be controlled and a large window for bigger changes of the signal to be controlled.
Each of the at least first and second comparator means corresponds to one of the limits of the at least one error signal window and provides as output a digital control signal indicative for the relation of the error signal to the respective limit. Thus, the resultant control signal is a quantized signal.
In one embodiment the error amplifying means is an operational amplifier configured to multiply the error between the detected signal and the first reference signal by a predetermined factor and wherein the error signal comprises the first reference signal as offset. Thus the respective limits of the at least one error signal window can be symmetrically arranged around the offset determined by the first reference signal.
In a preferred application of the feedback circuit the signal detecting means are connected to the output of a power supply circuit and the quantized control signal is input to a control circuit of the power supply circuit, which may be digital controller or alike. The control circuit is configured to regulated the power supply circuit such that the output signal stays within the at least one predetermined error signal window. In one embodiment the power supply circuit is a DC-DC-converter.
The afore mentioned object of the invention is further solved by a method for generating a quantized control signal from a sensed signal. Accordingly, the method comprises the steps of: determining at least one error signal window with predetermined upper and lower limits; generating a error signal by subtracting a reference signal from the input signal; amplifying the error signal; comparing the amplified error signal with the upper and lower limits of the at least one error window; and outputting the results of the comparing step as the quantized control signal.
The method may further comprise the step of dividing the input signal by a predetermined ratio. By this step the internal control signals of a circuit, in which the method is used, can be lower then an available supply voltage, which may be a battery. Further, the amplifying step may further comprise adding the reference signal to the amplified error signal as an offset. By this step the error signal windows do not need to by symmetrical to a ground reference potential of the circuit, by which generation of symmetrical reference signals can be avoided.
The method of the invention may advantageously be used in an electronic circuit for generating a quantized feedback signal from an output signal of the electronic circuit for control of the output signal.
To summarize, the general concept of the present invention resides in the idea that by use of one accurate error amplifier for amplification of the error signal, the needed window comparators can be relatively inaccurate, which reduces the requirements thereof. Moreover, with the method and respective circuit arrangement of the invention the error window size(s) can be much more accurate compared to the solution discussed above. This is important especially in situations where extremely small windows are needed for very accurate output voltages.